A Small Depth-16 Circuit for the AES S-Box
Joan Boyar, René Peralta

New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [Nogami, Nekado, Toyota, Hongo, Morikawa, 2010].

Last modified: Thu Mar 1 13:58:08 CET 2012